The present invention relates to semiconductor circuit devices implemented by integration of a large number of MIS transistors, and in particular relates to measures to reduce variations in transistor characteristics.
In recent years, an LSI (Large Scale Integration), as typified by a microprocessor, has generally been implemented by combining a large number of units each of which has a basic function and is called a cell. In each cell, numerous elements such as MIS transistors, capacitors and resistors are provided. As the performance and packing density of an LSI are increased, the circuit design for cells that determine the performance of an LSI is becoming very important. Furthermore, in carrying out the circuit design for cells with high precision, a CAD (Computer Aided Design) tool plays an extremely important role.
As a CAD tool deeply concerned in design accuracy, a circuit simulator is known. A circuit simulator is used to carry out circuit simulation for cells and an LSI that have been designed. To be more specific, using a circuit simulator, conceivable circuit operations of the cells and LSI that are to be presumably fabricated according to the design are simulated based on a netlist including pieces of information concerning connections between associated elements such as transistors, capacitors and resistors, and pieces of information concerning characteristics of the elements such as transistor sizes, capacitance values and resistance values. For example, such a netlist can be extracted from mask layouts of designed cells by using a circuit extractor. As for pieces of information concerning transistor characteristics, in order to precisely reproduce complicated electrical characteristics of transistors in a circuit simulator, numerous expressions representing electrical characteristics (hereinafter, called “transistor model”) are now being developed. Besides, in order to reproduce a desired transistor characteristic using a transistor model, model parameters included in the transistor model must be optimized in accordance with the desired transistor characteristic (hereinafter, simply called “model parameter extraction”).
Described below are a layout of a cell provided in a conventional semiconductor circuit device and a transistor model used in designing a conventional cell.
First, the cell layout will be described by using a cell layout shown in FIG. 8 as an example.
FIG. 8 is a plan view schematically illustrating an exemplary layout of a conventional cell 100 provided in a part of a semiconductor substrate. The semiconductor substrate is provided with an N-well 102 and a P-well 103 that are adjacent to each other with a well boundary 110 located therebetween. The N-well 102 is provided with first through third PMIS active areas Rtp1 through Rtp3 surrounded by a trench isolation Ris. On the other hand, the P-well 103 is provided with first through third NMIS active areas Rtn1 through Rtn3 surrounded by the trench isolation Ris. Herein, the “PMIS active area” refers to an active area for a P-channel MIS transistor, while the “NMIS active area” refers to an active area for an N-channel MIS transistor. Although three active areas are exemplarily provided in each of the N-well 102 and the P-well 103 in FIG. 8, a considerably large number of active areas are provided in an actual semiconductor circuit device. The first, second and third PMIS active areas Rtp1, Rtp2 and Rtp3 are provided with gates 107 of P-channel transistors. On the other hand, the first, second and third NMIS active areas Rtn1, Rtn2 and RTn3 are provided with gates 109 of N-channel transistors. It should be noted that, like a known transistor, each gate has a so-called “insulated gate structure” formed by a gate insulating film and a gate electrode, although not shown.
The semiconductor substrate is further provided with: an N-type substrate active area 104 through which a power supply voltage is supplied to respective elements in the cell 100; and a P-type substrate active area 105 through which a reference electric potential is supplied to respective elements in the cell 100.
Parts of each active area, located on the sides of each gate, are defined as source/drain regions. Upon application of voltage between the source/drain regions and application of bias to each gate, a channel is formed in a part of each active area, located under each gate, and an electric current flows through the channel.
Since various cells are generally combined in an LSI, a distance between a width YN+ of the N-type substrate active area 104 extending in a Y-direction and a width YP+ of the P-type substrate active area 105 extending in the Y-direction, i.e., a distance Dsell between the N-type substrate active area 104 and the P-type substrate active area 105, is standardized at a common value for each group of cells. Furthermore, a layout rule for the process of forming the cell 100 specifies: a lower limit S1 of a distance between the N-type substrate active area 104 and the first through third PMIS active areas Rtp1 through Rtp3; a lower limit S2 of a distance between the first through third PMIS active areas Rtp1 through Rtp3 and the well boundary 110; a lower limit S3 of a distance between the well boundary 110 and the first through third NMIS active areas Rtn1 through Rtn3; and a lower limit S4 of a distance between the first through third NMIS active areas Rtn1 through Rtn3 and the P-type substrate active area 105. Accordingly, in the Y-direction, the first through third PMIS active areas Rtp1 through Rtp3 can be laid out within a range SP located at a distance of the lower limit S1 or more from the N-type substrate active area 104 and at a distance of the lower limit S2 or more from the well boundary 110. Similarly, in the Y-direction, the first through third NMIS active areas Rtn1 through Rtn3 can be laid out within a range SN located at a distance of the lower limit S3 or more from the well boundary 110 and at a distance of the lower limit S4 or more from the P-type substrate active area 105.
FIG. 9 is a diagram schematically illustrating the structure of a transistor for the description of a conventional transistor model. As shown in FIG. 9, the transistor model includes: an active area Rt surrounded by a trench isolation Ris; a gate electrode 112 straddling the active area Rt to reach the trench isolation Ris at both sides of the active area Rt; source/drain regions 114a and 114b located on the sides of the gate electrode 112 of the active area Rt; and a channel region 113 located under the gate electrode 112 of the active area Rt. As indicated by the hatching in FIG. 9, in the transistor model, the channel region 113 of the transistor is defined by a region at which the active area Rt and the gate electrode 112 are overlapped. In addition, in the transistor model, the current drive capability of the transistor is determined by a width W (channel width) and a length L (channel length) of the channel region 113, an electric resistance of the active area Rt, and a load (not shown) added to the active area Rt, and information concerning the layout around the transistor is not taken into consideration.
The conventional semiconductor circuit device has been designed as described above because the design has been carried out on the assumption that the performance of the semiconductor circuit device is determined by the gate length and gate width of each transistor.
However, from the experiments carried out by the present inventors, it is found that the performance of a semiconductor circuit device provided with the latest miniaturized transistors might vary depending on not only the gate length and gate width of each transistor but also the layout of each active area. That is, even if circuit configurations are alike, the current drive capability of each transistor, for example, might vary depending on the layout, and therefore, the performance of an overall semiconductor circuit device is also affected by the layout. Accordingly, depending on a method for extracting model parameters of a transistor model used in designing the conventional cell 100, the performance of a semiconductor circuit device formed based on the design often falls short of the design goal, and it is difficult to maintain the design accuracy of the semiconductor circuit device at a high level.
A compressive stress applied from a trench isolation to a channel region (which will be hereinafter called a “trench isolation stress”) affects transistor characteristics in such a manner that a difference occurs between the performances of transistors having identical gate lengths and gate widths. How a trench isolation stress affects transistor characteristics will be described below. In a channel region of each transistor, a lattice strain occurs due to a trench isolation stress. Therefore, in an N-channel transistor, an effective mobility in a channel portion is decreased, and the performance of the N-type transistor tends to be reduced. In a P-type transistor, an effective mobility is also decreased in a channel portion due to a trench isolation stress applied in a gate width direction.
Suppose that one transistor is provided in one active area and the other transistor is provided in the other active area located adjacent to the one active area. In that case, if a distance between the one transistor and the other active area is varied, in particular, in a channel width direction, the transistors might exhibit different current drive capabilities.
Even if the transistors have identical channel widths and identical channel lengths, a difference occurs between the current drive capabilities of the transistors due to a variation in a distance between the one transistor and the other active area located adjacent to the one active area in which the one transistor is provided. Hereinafter, how this difference occurs will be described in detail with reference to FIG. 10. FIG. 10 is a plan view illustrating the layout for circuit simulation of the conventional semiconductor circuit device.
As shown in FIG. 10, three kinds of P-channel transistors TrpA, TrpB and TrpC have identical channel lengths and identical channel widths Wp. Three kinds of N-channel transistors TrnA, TrnB and TrnC also have identical channel lengths and identical channel widths Wn. A distance DpA between an active area RtpA, in which the transistor TrpA is located, and an N-type substrate active area 104 is equal to a distance DpC between an active area RtpC, in which the transistor TrpC is located, and the N-type substrate active area 104, while the distance DpA is different from a distance DpB between an active area RtpB, in which the transistor TrpB is located, and the N-type substrate active area 104. A distance DpnA between the active area RtpA and an active area RtnA is different from a distance DpnB between the active area RtpB and an active area RtnB. A distance DpnC between the active area RtpC and an active area RtnC is equal to the distance DpnB between the active area RtpB and the active area RtnB. A distance DnA between the active area RtnA and a P-type substrate active area 105 is equal to a distance DnB between the active area RtnB and the P-type substrate active area 105. And a distance DnC between the active area RtnC and the P-type substrate active area 105 is different from the distance DnA and the distance DnB.
In the above-described layout, the characteristics of the transistors TrpA through TrpC and the transistors TrnA through TrnC will be compared.
First, a comparison is made between the characteristic of the P-channel transistor TrpA and that of the P-channel transistor TrpB. The characteristic of the P-channel transistor TrpA facing the N-channel transistor TrnA in a Y-direction is determined by the channel length and the channel width Wp of the P-channel transistor TrpA, the distance DpA and the distance DpnA. The characteristic of the P-channel transistor TrpB facing the N-channel transistor TrnB in the Y-direction is determined by the channel length and the channel width Wp of the P-channel transistor TrpB, the distance DpB and the distance DpnB. The distance DnA between the active area RtnA, in which the N-channel transistor TrnA is located, and the P-type substrate active area 105 is equal to the distance DnB between the active area RtnB, in which the N-channel transistor TrnB is located, and the P-type substrate active area 105. That is, the N-channel transistors TrnA and TrnB are located similarly with respect to the Y-direction in the cell 100. In this layout, the following formulasDpA≠DpBDpnA≠DpnBhold true. In the Y-direction, the distance DpnA between the active area in which the P-channel transistor TrpA is located and another active area located adjacent thereto is different from the distance DpnB between the active area in which the P-channel transistor TrpB is located and another active area located adjacent thereto. Therefore, different trench isolation stresses are applied to the channel regions of the two P-channel transistors TrpA and TrpB. As a result, a difference occurs between the characteristics, e.g., the current drive capabilities, of the two P-channel transistors TrpA and TrpB. Even though the two NMIS active areas facing the two PMIS active areas are located similarly with respect to the Y-direction, the PMIS active areas are located differently with respect to the Y-direction. Therefore, the characteristics, e.g., the current drive capabilities, of the P-channel transistors located in the two PMIS active areas are varied in accordance with the distances between the PMIS active areas and the NMIS active areas in the Y-direction.
Next, a comparison is made between the characteristic of the P-channel transistor TrpA and that of the P-channel transistor TrpC. The characteristic of the P-channel transistor TrpC facing the N-channel transistor TrnC in the Y-direction is determined by the channel length and the channel width Wp of the P-channel transistor TrpC, the distance DpC and the distance DpnC. The distance DpA between the active area RtpA, in which the P-channel transistor TrpA is located, and the N-type substrate active area 104 is equal to the distance DpC between the active area RtpC, in which the P-channel transistor TrpC is located, and the N-type substrate active area 104. That is, the P-channel transistors TrpA and TrpC are located similarly with respect to the Y-direction in the cell 100. Therefore, the following formulaDpA=DpCholds true. However, the following formulaDpnA≠DpnCalso holds true. In the Y-direction, the distance DpnA between the active area in which the P-channel transistor TrpA is located and another active area located adjacent thereto is different from the distance DpnC between the active area in which the P-channel transistor TrpC is located and another active area located adjacent thereto. Therefore, different trench isolation stresses are applied to the channel regions of the two P-channel transistors TrpA and TrpC. As a result, a difference occurs between the characteristics, e.g., the current drive capabilities, of the two P-channel transistors TrpA and TrpC. Even though the two PMIS active areas are located similarly with respect to the Y-direction, the NMIS active areas facing the PMIS active areas are located differently with respect to the Y-direction. Therefore, the characteristics, e.g., the current drive capabilities, of the P-channel transistors located in the two PMIS active areas are varied in accordance with the distances between the PMIS active areas and the NMIS active areas in the Y-direction.
Next, a comparison is made between the characteristic of the P-channel transistor TrpB and that of the P-channel transistor TrpC. The distance DpnB between the active area RtpB, in which the P-channel transistor TrpB is located, and the active area RtnB, in which the N-channel transistor TrnB is located, is equal to the distance DpnC between the active area RtpC, in which the P-channel transistor TrpC is located, and the active area RtnC, in which the N-channel transistor TrnC is located. However, the distance DpB between the active area RtpB, in which the P-channel transistor TrpB is located, and the N-type substrate active area 104 is different from the distance DpC between the active area RtpC, in which the P-channel transistor TrpC is located, and the N-type substrate active area 104. Since the following formulaDpB≠DpCholds true, different trench isolation stresses are applied from the N-type substrate active area 104 to the P-channel transistors TrpB and TrpC, resulting in a difference between the characteristics of the transistors. Even though distances between the PMIS active areas, in which the two P-channel transistors are located, and the NMIS active areas facing the PMIS active areas in the Y-direction are identical, the characteristics, e.g., the current drive capabilities, of the P-channel transistors are varied if the active areas, in which the two P-channel transistors are provided, are located differently with respect to the Y-direction.
Although the description of the characteristic variations of the N-channel transistors are omitted, the characteristic variations of the N-channel transistors are similar to those of the P-channel transistors in that the greater the trench isolation stress in a channel region, the lower the current drive capability.
As described above, it can be understood that even if the conventional semiconductor circuit device is designed to allow the transistors to have identical channel lengths and identical channel widths, the characteristics of the transistors having identical channel widths in the cell 100 are considerably varied due to the trench isolation stress, thus making it difficult to realize the optimum LSI design.
Furthermore, in a method for extracting model parameters of a conventional transistor model, transistor characteristic variations due to the trench isolation stress cannot be taken into consideration in the transistor model itself, and therefore, the transistor characteristic variations in each cell cannot be reproduced, which increases errors in circuit simulation for each cell.